Low Power at Different Levels of Vlsi Design and Clock Disribution Schemes
نویسنده
چکیده
Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. In this paper various low power techniques at Gate level, Architecture level and different tradeoffs between different clock distribution schemes like as single driver clock scheme and distributed buffers clock scheme are reviewed. Here it is also tried to showing various effects of particular clock distribution scheme such as clock skew, clock jitter etc.
منابع مشابه
Low Power Clock Distribution Schemes in VLSI Design
This paper reviewed the comparison between different clock distribution schemes which used for low power VLSI design which are the most important aspect in the industry. The main clock distribution schemes are single driver clock scheme and distributed buffers clock scheme. There are different tradeoffs in both the techniques such as size of buffers, number of buffers etc.
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